QTEST — QSM Test Register
RR[0:F] — QSM Receive Data RAM
RSR — Reset Status Register
SCCR[0:1] — SCI Control Registers [0:1]
SCDR — SCI Data Register
SCSR — SCI Status Register
SIMCR — SIM Module Configuration Register
SIMTR — System Integration Test Register
SIMTRE — System Integration Test Register (ECLK)
SPCR[0:3] — QSPI Control Registers [0:3]
SPSR — QSPI Status Register
SWSR — Software Watchdog Service Register
SYNCR — Clock Synthesizer Control Register
SYPCR — System Protection Control Register
TCNT — Timer Counter Register
TCTL[1:2] — Timer Control Registers [1:2]
TFLG[1:2] — Timer Interrupt Flag Registers [1:2]
TI4/O5 — Timer Input Capture 4/Output Compare 5 Register
TIC[1:3] — Timer Input Capture Registers [1:3]
TMSK[1:2] — Timer Interrupt Mask Register [1:2]
TOC[1:4] — Timer Output Compare Registers [1:4]
TR[0:F] — QSM Transmit Data RAM
2
TSTMSRA — Test Module Master Shift Register A
TSTMSRB — Test Module Master Shift Register B
TSTRC — Test Module Repetition Count Register
TSTSC — Test Module Shift Count Register
2.5 Conventions
Logic level one is the voltage that corresponds to a Boolean true (1) state.
Logic level zero is the voltage that corresponds to a Boolean false (0) state.
Set refers specifically to establishing logic level one on a bit or bits.
Clear refers specifically to establishing logic level zero on a bit or bits.
Asserted means that a signal is in active logic state. An active low signal changes
from logic level one to logic level zero when asserted, and an active high signal chang-
es from logic level zero to logic level one.
Negated means that an asserted signal changes logic state. An active low signal
changes from logic level zero to logic level one when negated, and an active high sig-
nal changes from logic level one to logic level zero.
MOTOROLA
2-6
NOMENCLATURE
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
