on the first four rising edges of SCLK, and the previous 10-bit
conversion result is shifted out on the first nine falling edges
of SCLK. After the fourth rising edge of SCLK, the new mux
address is available; therefore, on the next edge of SCLK
(the fourth falling edge), the analog input voltage on the
selected mux input begins charging the RC DAC and con-
tinues to do so until the tenth falling edge of SCLK. After this
tenth SCLK edge, the analog input voltage is disabled from
the RC DAC and the RC DAC begins the “hold” portion of the
A/D conversion sequence. Also upon this tenth SCLK edge,
control of the internal circuitry is transferred to the internal
clock oscillator which drives the successive approximation
logic to complete the conversion. If 16 SCLK cycles are used
during each transfer, then there is a constraint on the mini-
mum SCLK frequency. Specifically, there must be at least
one rising edge on SCLK before the A/D conversion is com-
plete. If the SCLK frequency is too low and a rising edge
does not occur during the conversion, the chip is thrown out
of sync with the processor and CS needs to be toggled in or-
der to restore proper operation. If 10 SCLKs are used per
transfer, then there is no lower frequency limit on SCLK. Also
note that if the ADC is operated such that CS is inactive high
between transfers, then the number of SCLK cycles per
transfer can be anything between 10 and 16 cycles, but the
“rising edge” constraint is still in effect if more than 10 SCLKs
are used. (If CS stays active low for multiple transfers, the
number of SCLK cycles must be either 10 or 16.)
and leakage currents through the ESD protection diodes on
the selected channel occur. These leakage currents cause
an offset voltage to appear across any series source resis-
tance on the selected channel. Therefore, any source resis-
tance greater than 1 kΩ (Motorola test condition) may induce
errors in excess of guaranteed specifications.
There are three tests available that verify the functionality
of all the control logic as well as the successive approxima-
tion comparator. These tests are performed by addressing
$B, $C, or $D and they convert a voltage of (V + V )/2,
ref AG
V
, or V , respectively. The voltages are obtained internal-
ref
AG
ly by sampling V or V
ref AG
onto the appropriate elements of
the RC DAC during the sample phase. Addressing $B, $C, or
$D produces an output of $200 (half scale), $000, or $3FF
(full scale), respectively, if the converter is functioning prop-
erly. However, deviation from these values occurs in the
presence of sufficient system noise (external to the chip) on
V
, V , V , or V .
DD SS ref AG
POWER AND REFERENCE PINS
V
and V
DD
SS
Device Supply Pins (Pins 7 and 14)
V
is normally connected to digital ground; V
is con-
DD
SS
nected to a positive digital supply voltage. Low frequency
(V – V ) variations over the range of 4.5 to 5.5 volts do
DD
SS
not affect the A/D accuracy. (See the Operations Ranges
Table for restrictions on V and V relative to V and
EOC
ref AG
DD
lines, as on
End-of-Conversion Output (Pin 1)
V
.) Excessive inductance in the V
or V
DD SS
SS
EOC goes low on the tenth falling edge of SCLK. A low-to-
high transition on EOC occurs when the A/D conversion is
complete and the data is ready for transfer.
automatic test equipment, may cause A/D offsets > ± 1 LSB.
Use of a 0.1 µF bypass capacitor across these pins is recom-
mended.
ANALOG INPUTS AND TEST MODES
V
AG
and V
ref
Analog Reference Voltage Pins (Pins 8 and 9)
AN0 through AN4
Analog Multiplexer Inputs (Pins 2 – 6)
Analog reference voltage pins which determine the lower
and upper boundary of the A/D conversion. Analog input volt-
The input AN0 is addressed by loading $0 into the mux
address register. AN1 is addressed by $1, AN2 by $2, AN3
by $3, and AN4 by $4. Table 2 shows the input format for a
16-bit stream. The mux features a break-before-make
switching structure to minimize noise injection into the ana-
log inputs. The source resistance driving these inputs must
ages ≥ V
produce a full scale output and input voltages
ref
produce an output of zero. CAUTION: The analog
≤ V
AG
input voltage must be ≥ V
and ≤ V
. The A/D conversion
and V must be as
AG
SS
DD
result is ratiometric to V – V . V
noise-free as possible to avoid degradation of the A/D
conversion. Ideally, V and V should be single-point con-
nected to the voltage supply driving the system’s transduc-
ers. Use of a 0.22 µF bypass capacitor across these pins is
strongly urged.
ref AG ref
ref AG
be
1 kΩ.
During normal operation, leakage currents through the
analog mux from unselected channels to a selected channel
MC145053
7
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
MOTOROLA [ MOTOROLA ]
