MOSEL VITELIC
Pin Descriptions
A
0
–A
15
Address Inputs
These 16 address inputs select one of the 64K x 16
bit segments in the RAM.
CE
Chip Enable Input
CE is active LOW. It must be active to read from or
write to the device. If chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
Output Enable Input
The output enable input is active LOW. When OE
is Low with CE Low and WE High, data will be pre-
sented on the I/O pins. The I/O pins will be in the
high impedance state when OE is High.
V61C51161024
UBE, LEB Byte Enable
Active low inputs. These inputs are used to enable
the upper or lower data byte.
WE
Write Enable Input
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
I/O
0
–I/O
15
Data Input and Data Output Ports
These 16 bidirectional ports are used to read data
from and write data into the RAM.
V
CC
GND
Power Supply
Ground
Pin Configurations (Top View)
44-Pin SOJ
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
GND
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
6151161024-02
44-Pin TSOP-II (Standard)
A
5
A
6
A
7
OE
UBE
LBE
I/O
15
I/O
14
I/O
13
I/O
12
GND
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
6151161024-03
A5
A6
A7
OE
UBE
LBE
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
V61C51161024 Rev. 1.0 July 1998
2
MOSEL [ MOSEL VITELIC, CORP ]
