MOSEL VITELIC
V61C51161024
64K x 16 HIGH SPEED
STATIC RAM
PRELIMINARY
Features
s
s
s
s
s
s
High-speed: 10, 12, 15 ns
All inputs and outputs directly TTL compatible
Three state outputs
Byte Control Pins
Single 5V
±
10% Power Supply
Packages
– 44-pin TSOP (Standard)
– 44-pin 400 mil SOJ
Description
The V61C51161024 is a 1,048,576-bit static
random-access memory organized as 65,536
words by 16 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing with
common system bus structures.
Functional Block Diagram
A
1
Row
Decoder
Memory Array
V
CC
GND
A
7
A
8
A
9
I/O
0
Input
Data
Circuit
I/O
15
A
0
UBE
LBE
OE
WE
CE
Column I/O
Column Decoder
A
10
A
15
Control
Circuit
6151161024-01
Device Usage Chart
Operating
Temperature
Range
0
°C
to 70
°C
Package Outline
T
•
K
•
10
•
Access Time (ns)
12
•
15
•
Temperature
Mark
Blank
V61C51161024 Rev. 1.0 July 1998
1