V58C2128(804/404/164)S
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA
0
(The DDR SDRAM should be
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A
0
~ A
11
in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock
cycles are required to meet t
MRD
spec. The mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-
ister is divided into various fields depending on functionality. The burst length uses A
0
~ A
2
, addressing mode
uses A
3
, CAS latency (read latency from column address) uses A
4
~ A
6
. A
7
is a Mosel Vitelic specific test
mode during production test. A
8
is used for DLL reset. A
7
must be set to low for normal MRS operation. Refer
to the table for specific codes for various burst length, addressing modes and CAS latencies.
1. MRS can be issued only at all banks precharge state.
2. Minimum tRP is required to issue MRS command.
CILETIV LESO M
Mode Register Set (MRS)
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
0
MRS
RFU : Must be set "0"
QFC I/O
DLL
Extended Mode Register
Mode Register
0
MRS
RFU
DLL
TM
CAS Latency
BT
Burst Length
A
8
0
1
BA
0
0
1
A
n
~ A
0
DLL Reset
No
Yes
A
7
0
1
mode
Normal
Test
A
4
0
1
0
1
0
1
0
1
Latency
Reserve
Reserve
2
3
Reserve
Reserve
2.5
Reserve
A
3
0
1
Burst Type
Sequential
Interleave
Burst Length
A
2
0
0
0
0
1
1
1
1
A
1
0
0
1
1
0
0
1
1
A
0
0
1
0
1
0
1
0
1
A
1
0
1
I/O Strength
Full
Half
A
0
0
1
DLL Enable
Enable
Disable
CAS Latency
A
6
A
5
0
0
0
0
1
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
1
1
1
0
0
1
1
0
0
1
1
(Existing)MRS Cycle
Extended Funtions(EMRS)
Latency
Sequential
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
Interleave
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
A
2
0
1
QFC Control
Disable
Enable
Mode Register Set
0
CK, CK
Command
t
CK
1
2
3
*1
Mode
Register Set
4
5
6
7
8
Precharge
All Banks
Any
Command
t
RP
*2
t
MRD
V58C2128(804/404/164)S Rev. 1.6 March 2002
7
MOSEL [ MOSEL VITELIC, CORP ]
