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V58C2128404S 参数 Datasheet PDF下载

V58C2128404S图片预览
型号: V58C2128404S
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能2.5伏128兆位的DDR SDRAM [HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 59 页 / 922 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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V58C2128(804/404/164)S  
Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK)  
During Read Cycles  
(CAS Latency = 2.5; Burst Length = 4)  
T4  
T0  
T1  
T2  
T3  
CK, CK  
READ  
NOP  
NOP  
NOP  
NOP  
Command  
t
(max)  
DQSCK  
t
(min)  
DQSCK  
DQS  
DQ  
t
(max)  
AC  
t
(min)  
AC  
D
D
D
D
3
0
1
2
The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a mem-  
ory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to  
the output data. The minimum data output valid time (tDV) and minimum data strobe valid time (tDQSV) are de-  
rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to  
DLL jitter and power supply noise.  
V58C2128(804/404/164)S Rev. 1.6 March 2002  
10