V54C316162VC
5. Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
I/O’s
DIN A
0
don’t care
DIN A
DIN A
DIN A
3
1
2
The first data element and the Write
are registered on the same clock edge.
Extra data is ignored after
termination of a Burst.
5.1 Write to Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
PRE
NOP
NOP
NOP
NOP
WRITE
COMMAND
NOP
tRDL
I/O’S
DIN A0
DIN A1
DIN A2
DIN A3
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
WRITE B
DIN B0
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
I/O’s
tCDL
DIN A0
DIN B1
DIN B2
DIN B3
V54C316162VC Rev. 1.4 December 2001
17