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V54C3128804VAT7 参数 Datasheet PDF下载

V54C3128804VAT7图片预览
型号: V54C3128804VAT7
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能133分之143 / 125MHz的3.3伏16M ×8的同步DRAM 4组X的4Mbit ×8 [HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8]
分类和应用: 内存集成电路光电二极管动态存储器时钟
文件页数/大小: 43 页 / 362 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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MOSEL VITELIC
Operation Definition
V54C3128804VAT
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Operation
Row Activate
Read
Read w/Autoprecharge
Write
Write with Autoprecharge
Row Precharge
Precharge All
Mode Register Set
No Operation
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Device
State
Idle
3
Active
3
Active
3
Active
3
Active
3
Any
Any
Idle
Any
Any
Idle
Idle
Idle
(Self Refr.)
Idle
Active
5
Any
(Power
Down)
Active
Active
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
H
CKE
n
X
X
X
X
X
X
X
X
X
X
H
L
CS
L
L
L
L
L
L
L
L
L
H
L
L
H
RAS
L
H
H
H
H
L
L
L
H
X
L
L
X
H
X
H
X
H
X
X
CAS
H
L
L
L
L
H
H
L
H
X
L
L
X
H
X
H
X
H
X
X
WE
H
H
H
L
L
L
L
L
H
X
H
H
X
X
X
X
X
L
X
X
DQM
X
X
X
X
X
X
X
X
X
X
X
X
A0-9,
A11
V
V
V
V
V
X
X
V
X
X
X
X
A10
V
L
H
L
H
L
H
V
X
X
X
X
BS0
BS1
V
V
V
V
V
V
X
V
X
X
X
X
L
H
L
H
X
X
X
X
Power Down Entry
H
L
L
H
X
X
X
X
Power Down Exit
L
H
L
X
X
X
X
X
X
Data Write/Output Enable
Data Write/Output Disable
H
H
X
X
L
H
X
X
X
X
X
X
Notes:
1. V = Valid , x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Power Down Mode can not entry in the burst cycle.
V54C3128804VAT Rev. 1.4 November 2000
5