MOSEL VITELIC
V 54
MOSEL-VITELIC
MANUFACTURED
SYCHRONOUS
DRAM FAMILY
C = CMOS PROCESS
3.3V, LVTTL, INTERFACE
DEVICE
NUMBER
V54C3128804VAT
C
31
28804
V
A
T
SPEED
PWR.
7 ns
8 ns
BLANK (STANDARD)
T = TSOP-II
A = A VERSION
V = LVTTL
PKG
Description
TSOP-II
Pkg.
T
Pin Count
54
4 BANKS x 4Mbit x 8 (4K REFRESH)
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
V
CC
I/O
1
V
CCQ
NC
I/O
2
V
SSQ
NC
I/O
3
V
CCQ
NC
I/O
4
V
SSQ
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Pin Names
CLK
CKE
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for I/O’s (+3.3V)
Ground for I/O’s
Not connected
V
SS
I/O
8
V
SSQ
NC
I/O
7
V
CCQ
NC
I/O
6
V
SSQ
NC
I/O
5
V
CCQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
CS
RAS
CAS
WE
A
0
–A
11
BA0, BA1
I/O
1
–I/O
8
DQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
V54C3128804VAT Rev. 1.4 November 2000
2
MOSEL [ MOSEL VITELIC, CORP ]
