V54C3128(16/80/40)4V(T/S)
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Device
State
CKE CKE
A0-9,
BS0
BS1
Operation
Row Activate
n-1
n
X
X
X
X
X
X
X
X
X
X
H
L
CS
L
RAS CAS WE DQM A11 A10
Idle3
Active3
Active3
Active3
Active3
Any
H
L
H
H
H
H
L
H
L
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
X
X
V
X
X
X
X
V
L
V
V
V
V
V
V
X
V
X
X
X
X
Read
H
L
Read w/Autoprecharge
Write
H
L
L
H
L
H
L
L
Write with Autoprecharge
Row Precharge
Precharge All
H
L
L
L
H
L
H
L
H
H
L
L
Any
H
L
L
L
H
V
X
X
X
X
Mode Register Set
No Operation
Idle
H
L
L
L
Any
H
L
H
X
L
H
X
L
H
X
H
H
X
X
X
X
X
L
Device Deselect
Auto Refresh
Any
H
H
L
Idle
H
Self Refresh Entry
Self Refresh Exit
Idle
H
L
L
L
Idle
H
L
X
H
X
H
X
H
X
H
X
H
X
H
(Self Refr.)
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
Power Down Entry
Power Down Exit
Idle
Active4
H
L
Any
H
L
(Power
Down)
H
Data Write/Output Enable
Data Write/Output Disable
Active
Active
H
H
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
H
Notes:
1. V = Valid , x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BS0, BS1 signals.
4. Power Down Mode can not entry in the burst cycle.
V54C3128(16/80/40)4V(T/S) Rev.1.2 August 2002
10
MOSEL [ MOSEL VITELIC, CORP ]
