MO SEL VITELIC
V53C816H
any data stored in the output latches. A WE low lev-
el can also disable the output drivers when CAS is
low. During a Write cycle, if WE goes low at a time
in relationship to CAS that would normally cause the
outputs to be active, it is necessary to use OE to dis-
able the output drivers prior to the WE low transition
Table 1. V53C816H Data Output
Operation for Various Cycle Types
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
to allow Data In Setup Time (t ) to be satisfied.
CAS-Controlled Write
Cycle (Early Write)
High-Z
DS
Power-On
WE-Controlled Write
Cycle (Late Write)
OE Controlled. High
OE = High-Z I/Os
After application of the V
supply, an initial
CC
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
Read-Modify-Write Cycles
Data from Addressed
Memory Cell
Fast Page Mode Read
Data from Addressed
Memory Cell
During Power-On, the V current requirement of
the V53C816H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
Fast Page Mode Write
Cycle (Early Write)
High-Z
CC
Fast Page Mode Read-
Modify-Write Cycle
Data from Addressed
Memory Cell
device will go into an active cycle and I will exhibit
CC
current transients. It is recommended that RAS and
RAS-only Refresh
High-Z
CAS track with V or be held at a valid V during
CC
IH
CAS-before-RAS Refresh
Cycle
Data remains as in
previous cycle
Power-On to avoid current surges.
CAS-only Cycles
High-Z
V53C816H Rev. 1.3 February 1999
16
MOSEL [ MOSEL VITELIC, CORP ]
