MO SEL VITELIC
V53C816H
Functional Description
Fast Page Mode Operation
The V53C816H is a CMOS dynamic RAM opti-
mized for high data bandwidth, low power applica-
tions. It is functionally similar to a traditional
dynamic RAM. The V53C816H reads and writes
data by multiplexing an 19-bit address into a 10-bit
row and a 9-bit column address. The row address is
latched by the Row Address Strobe (RAS). The col-
umn address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
Fast Page Mode operation permits all 512 col-
umns within a selected row of the device to be ran-
domly accessed at a high data rate. Maintaining
RAS low while performing successive CAS cycles
retains the row address internally and eliminates the
need to reapply it for each cycle. The column ad-
dress buffer acts as a transparent or flow-through
latch while CAS is high. Thus, access begins from
the occurrence of a valid column address rather
than from the falling edge of CAS, eliminating t
ASC
and t from the critical timing path. CAS latches the
T
address into the column address buffer and acts as
an output enable. During Fast Page Mode opera-
tion, Read, Write, Read-Modify-Write or Read-
Write-Read cycles are possible at random address-
es within a row. Following the initial entry cycle into
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be end-
Fast Page Mode, access is t
or t
controlled.
CAA
CAP
ed or aborted before the minimum t
pired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
time has ex-
If the column address is valid prior to the rising edge
of CAS, the access time is referenced to the CAS
RAS
rising edge and is specified by t
. If the column
CAP
the minimum precharge time t /t has elapsed.
address is valid after the rising CAS edge, access
is timed from the occurrence of a valid address and
RP CP
is specified by t
. In both cases, the falling edge
Read Cycle
CAA
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS opera-
tion. The column address must be held for a mini-
of CAS latches the address and enables the output.
Fast Page Mode provides a sustained data rate of
43 MHz for applications that require high data rates
such as bit-mapped graphics or high-speed signal
processing. The following equation can be used to
calculate the maximum data rate:
mum specified by t . Data Out becomes valid only
AR
when t
, t
, t
and t
are all satisifed. As
OAC RAC CAA
CAC
a result, the access time is dependent on the timing
relationships between these parameters. For exam-
512
ple, the access time is limited by t
when t
,
CAA
RAC
Data Rate = ----------------------------------------
t
and t
are all satisfied.
t
+ 511 × t
CAC
OAC
RC PC
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column ad-
dress is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
Data Output Operation
The V53C816H Input/Output is controlled by OE,
CAS, WE and RAS. A RAS low transition enables
the transfer of data to and from the selected row ad-
dress in the Memory Array. A RAS high transition
disables data transfer and latches the output data if
the output is enabled. After a memory cycle is initi-
ated with a RAS low transition, a CAS low transition
or CAS low level enables the internal I/O path. A
CAS high transition or a CAS high level disables the
I/O path and the output driver if it is enabled. A CAS
low transition while RAS is high has no effect on the
I/O data path or on the output drivers. The output
drivers, when otherwise enabled, can be disabled
by holding OE high. The OE signal has no effect on
the high state and t
must be satisfied.
OED
V53C816H Rev. 1.3 February 1999
15
MOSEL [ MOSEL VITELIC, CORP ]
