MOSEL VITELIC
V53C8129H
Functional Description
Refresh Cycle
The V53C8129H is a CMOS dynamic RAM opti-
mized for high data bandwidth, low power applica-
tions. It is functionally similar to a traditional
dynamic RAM. The V53C8129H reads and writes
data by multiplexing an 17-bit address into a 8-bit
row and an 9-bit column address. The row address
is latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
To retain data, 512 Refresh Cycles are required
in each 8 ms period. There are two ways to refresh
the memory:
1. By clocking each of the 512 row addresses (A
0
through A ) with RAS at least once every 8 ms.
8
Any Read, Write, Read-Modify-Write or RAS-
only cycle refreshes the addressed row.
2. Using a CAS-before-RAS Refresh Cycle. If CAS
makes a transition from low to high to low after
the previous cycle and before RAS falls, CAS-
before-RAS
refresh
is
activated.
The
V53C8129H uses the output of an internal 9-bit
counter as the source of row addresses and ig-
nore external address inputs.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be end-
CAS-before-RAS is a “refresh-only” mode and no
data access or device selection is allowed. Thus,
the output remains in the High-Z state during the cy-
cle. A CAS-before-RAS counter test mode is provid-
ed to ensure reliable operation of the internal
refresh counter.
ed or aborted before the minimum t
time has ex-
RAS
pired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time t /t has elapsed.
RP CP
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS opera-
tion. The column address must be held for a mini-
Extended Data Out Page Mode
The V53C8129H offers fast access within a row.
Unlike ordinary fast page mode DRAM, the
V53C8129H output remains active and valid even
after CAS goes high and it will stay valid for 5ns af-
ter CAS changes low. The feature allows the
V53C8129H to CAS cycle faster than ordinary page
mode DRAM since the cycle time be short as data
access time.
mum specified by t . Data Out becomes valid only
AR
when t
, t
, t
and t
are all satisifed. As
OAC RAC CAA
CAC
a result, the access time is dependent on the timing
relationships between these parameters. For exam-
ple, the access time is limited by t
when t
,
CAA
RAC
t
and t
are all satisfied.
CAC
OAC
The outputs are disabled at the tHZ time after
RAS and CAS are high. The tHZ time is referenced
from rising edge of RAS or CAS whichever occurs
last. In addition, high on OE input and activation of
the write-cycle will also disable the outputs.
The following equation can be used to calculate
the maximum data rate:
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column ad-
dress is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
256
Data Rate = ----------------------------------------
t
+ 255 × t
RC
PC
the high state and t
must be satisfied.
OED
V53C8129H Rev. 1.3 July 1997
14
MOSEL [ MOSEL VITELIC, CORP ]
