MO SEL VITELIC
V53C8125H
V
5
3
C
8
1
2
5
H
FAMILY
DEVICE
PKG SPEED
( t
TEMP.
PWR.
)
RAC
BLANK (0°C to 70°C)
BLANK (NORMAL)
K (SOJ)
T (TSOP)
Description Pkg. Pin Count
30 (30 ns)
35 (35 ns)
40 (40 ns)
45 (45 ns)
50 (50 ns)
SOJ
K
T
26/24
28
8125H 01
TSOP-II
26/24 Lead SOJ
PIN CONFIGURATION
Top View
28 Lead TSOP-I
PIN CONFIGURATION
Top View
V
1
2
3
4
5
6
26
25
24
23
22
21
V
SS
SS
CAS
I/O5
I/O6
I/O7
I/O8
VSS
VSS
NC
I/O1
I/O2
I/O3
I/O4
NC
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A8
A7
A6
A5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
2
3
4
8
7
6
5
A4
NC
VCC
NC
A3
A2
A1
WE
CAS
9
10
11
12
13
14
RAS
8
19
18
17
16
15
14
OE
A
9
A
8
0
A
1
10
11
12
13
A
A0
RAS
7
WE
A
A
6
2
A
3
A
5
8125H 03
V
A
4
CC
8125H 02
Pin Names
A -A
Address Inputs (A : Column Address only)
0
8
8
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Write Enable
OE
Output Enable
Data Input, Output
+5V Supply
I/O - I/O
1
CC
SS
8
V
V
0V Supply
NC
No Connect
V53C8125H Rev. 1.7 August 1998
2