MO SEL VITELIC
V53C16258H
Functional Description
Extended Data Output Page Mode
The V53C16258H is a CMOS dynamic RAM
optimized for high data bandwidth, low power
applications. It is functionally similar to a traditional
dynamic RAM. The V53C16258H reads and writes
data by multiplexing an 18-bit address into a 9-bit
row and a 9-bit column address. The row address is
latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
EDO Page operation permits all 512 columns
within a selected row of the device to be randomly
accessed at a high data rate. Maintaining RAS low
while performing successive CAS cycles retains the
row address internally and eliminates the need to
reapply it for each cycle. The column address buffer
acts as a transparent or flow-through latch while
CAS is high. Thus, access begins from the
occurrence of a valid column address rather than
from the falling edge of CAS, eliminating t
and t
ASC
T
from the critical timing path. CAS latches the
address into the column address buffer. During
EDO operation, Read, Write, Read-Modify-Write or
Read-Write-Read cycles are possible at random
addresses within a row. Following the initial entry
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be
cycle into Hyper Page Mode, access is t
or t
CAA
CAP
controlled. If the column address is valid prior to the
rising edge of CAS, the access time is referenced to
the CAS rising edge and is specified by t
ended or aborted before the minimum t
time has
RAS
expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
. If the
CAP
column address is valid after the rising CAS edge,
access is timed from the occurrence of a valid
the minimum precharge time t /t has elapsed.
RP CP
address and is specified by t
. In both cases, the
CAA
Read Cycle
falling edge of CAS latches the address and
enables the output.
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS
operation. The column address must be held for a
EDO provides a sustained data rate of 83 MHz for
applications that require high bandwidth such as bit-
mapped graphics or high-speed signal processing.
The following equation can be used to calculate the
maximum data rate:
minimum specified by t . Data Out becomes valid
only when t
satisifed. As a result, the access time is dependent
on the timing relationships between these
parameters. For example, the access time is limited
AR
, t
, t
and t
are all
OAC
RAC
CAA
CAC
512
by t
when t
, t
and t
are all satisfied.
CAA
RAC CAC
OAC
Data Rate = ----------------------------------------
t
+ 511 × t
RC
PC
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column
address is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
Self Refresh
Self Refresh mode provides internal refresh con-
trol signals to the DRAM during extended periods of
inactivity. Device operation in this mode provides
additional power savings and design ease by elimi-
nation of external refresh control signals. Self Re-
fresh mode is initiated with a CAS before RAS
(CBR) Refresh cycle, holding both RAS low (t
and CAS low (t
)
RASS
) for a specified period. Both of
CHD
these parameters are specified with minimum val-
ues to guarantee entry into Self Refresh operation.
Once the device has been placed in to Self Refresh
mode the CAS clock is no longer required to main-
tain Self Refresh operation.
the high state and t
must be satisfied.
OED
V53C16258H Rev. 3.8 November 1999
16
MOSEL [ MOSEL VITELIC, CORP ]
