V437464S24V
AC Characteristics 3,4
T = 0° to 70°C; V = 0V; V = 3.3V ± 0.3V, t = 1 ns
A
SS
CC
T
-75PC
-75
-10PC
# Symbol Parameter
Clock and Clock Enable
Min. Max. Min. Max. Min. Max. Unit Note
1
2
3
tCK
fCK
tAC
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
7.5
7.5
7.5
10
10
10
ns
ns
System frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
133
–
–
133
100
–
–
100
100
MHz
MHz
Clock Access Time
CAS Latency = 3
CAS Latency = 2
4,5
–
–
5.4
6
–
–
5.4
6
–
–
6
6
ns
ns
4
5
tCH
tCL
tCS
tCH
Clock High Pulse Width
Clock Low Pulse Width
Input Setup time
2.5
2.5
1.5
0.8
2.5
8
–
–
–
–
–
–
–
2.5
2.5
1.5
0.8
2.5
8
–
–
–
–
–
–
–
3
3
2
1
2
8
1
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
6
6
7
7
8
9
6
7
Input Hold Time
8
tCKSP CKE Setup Time (Power down mode)
tCKSR CKE Setup Time (Self Refresh Exit)
9
10
tT
Transition time (rise and fall)
1
1
Common Parameters
11
12
13
14
15
16
tRCD
tRC
tRAS
tRP
tRRD
tCCD
RAS to CAS delay
15
70
42
15
14
1
–
–
–
–
–
–
20
60
45
20
15
1
–
–
–
–
–
–
20
60
45
20
20
1
–
–
–
–
–
–
ns
ns
Cycle Time
Active Command Period
Precharge Time
ns
ns
Bank to Bank Delay Time
CAS to CAS delay time (same bank)
ns
CLK
Refresh Cycle
10
64
10
64
10
64
17 tSREX Self Refresh Exit Time
–
–
–
–
–
–
ns
9
8
18
tREF
Refresh Period (8192 cycles)
ms
Read Cycle
19
20
21
22
tOH
tLZ
Data Out Hold Time
3
0
3
2
–
–
3
0
3
2
–
–
3
0
3
2
–
–
ns
ns
4
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
tHZ
7.5
–
7.5
–
7.5
–
ns
10
tDQZ
CLK
Write Cycle
23
24
25
tDPL
tDAL
Data input to Precharge (write recovery)
Data In to Active/refresh
2
5
0
–
–
–
2
5
0
–
–
–
1
5
0
–
–
–
CLK
CLK
CLK
11
tDQW
DQM Write Mask Latency
V437464S24V Rev. 1.0 January 2002
8
MOSEL [ MOSEL VITELIC, CORP ]
