MO SEL VITELIC
MSU2051/U2031
Data Memory Read Cycle Timing
T12
T1
T2
T3
T4
T5
T6
T7
T8 T9
T10 T11 T12 T1
T2
T3
OSC
1
2
ALE
#PSEN
#RD
5
7
3
ADDRESS A - A
15
PORT2
PORT0
8
3
4
6
8
INST in Float
A
-A
Float
DATA in
Float
ADDRESS
or Flloat
7
0
Program Memory Read Cycle Timing
T12 T1
T2
T3
T4
T5
T6
T7
T8 T9
T10 T11 T12 T1
T2
OSC
1
2
ALE
5
7
#PSEN
#RD, #WR
PORT2
PORT0
3
ADDRESS A - A
15
ADDRESS A -A
15
8
8
3
4
6
8
Float
A
-A
Float
INST in
Float
A
-A
Float
INST in
Float
7
0
7
0
Rev. 1.0 February 1998
10