SYS88000RKX-85/10/12
ISSUE 1.5 : April 2001
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
I/O Pin
Ω
645
1.76V
100pF
* VCC=5V±10%
Operation Truth Table
CS
H
L
OE
X
WE
X
DATA PINS
High Impedance
Invalid State
Data Out
SUPPLY CURRENT
MODE
Standby
Invalid
Read
ISB1 , ISB2 , ISB3, ISB4
L
L
~
L
L
H
ICC1
ICC1
ICC1
L
H
H
L
Data In
Write
L
H
High-Impedance
High-Z
Notes : H = VIH
: L =VIL : X = VIH or VIL
OE must not be tied low permanently.
Low Vcc Data Retention Characteristics - L Version Only
Parameter
Symbol
Test Condition
CS > VCC-0.2V
min
2.0
typ(1) max
Unit
VCC for Data Retention
Data Retention Current
VDR
-
-
-
-
-
2
-
V
mA
ns
(2)
ICCDR1
VCC = 3.0V, CS > VCC-0.2V
See Retention Waveform
See Retention Waveform
-
0
Chip Deselect to Data Retention Time tCDR
Operation Recovery Time
tR
5.0
-
ms
Notes
(1)
Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
(3) Add 840mA to -L CMOS standby currents to obtain industrial temp range parameters.
3
MOSAIC [ MOSAIC ]
