ISSUE 4.3 : November 1998
PUMA 68F16006/A-80/90/12/15
D6
Toggle Bit
The device also features the "toggle bit" as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read data from the device
will result in D6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is
completed, D6 will stop toggling and valid data will be read on successive attempts. During programming, the
Toggle bit is valid after the rising edge of the forth WE pulse in the four write pulse sequence. For chip erase,
the Toggle bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during
the sector time-out.
D5 Exceeding Time Limits
D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will
produce "1", indicating the program or erase cycle was not successfully completed . Data Polling is the only
operating function of the device under this condition. The CE circuit will partially power down the device under
these conditions (to approximately 2mA). The OE and WE pins will control the output disable functions . To
reset the device, write reset command sequence to the device. This allows the system to continue to use the
other active sectors in the device, if this failure occurs during sector erase operations, it specifies that a par-
ticular sector is bad and may not be re-used. The device must be reset to use other sectors. While the reset
command sequence and execute program or erase command sequence.
If this failure occurs during chip erase operation , it specifies that the device chip or combination of sectors are
bad. If this failure occurs during the byte programming operation, it specifies that the active sectors containing
that byte is bad and may not be re-used.
The D5 failure condition may also appear if the user tries to program a non blank location without erasing. In
this case the device locks out and never completes the embedded algorithm operation. Hence the system
never reads a valid data on D7 and D6 never stops toggling. Once the device has exceeded timing limits, the
D5 bit will indicate '1'
D4 Hardware Sequence Flag
If the device has exceeded the specified erase or program time and D5 is "1", then D4 will indicate at which
step in the algorithm the device exceeded the limits. A "0" in D4 indicates in programming, a "1" indicates an
erase.
D3 Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3
will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may
be used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase
cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase opera-
tion is completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional
sector erase commands. To insure the command has been accepted, the software should check the status of
D3 prior to and following each subsequent sector erase command. If D3 were high on the second status
check, the command may not have been accepted.
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MOSAIC [ MOSAIC ]
