PUMA2SV16000AMB-025 参数 Datasheet PDF下载

PUMA 2/77SV16000 - 020/025/35

Issue 1.0 : January 2000

Capacitance

(V

CC

=3.3V±10%,T

A

=25°C)

Note: These parameters are calculated and not measured.

Parameter

Input Capacitance Address, OE

WE1~4, CS1~4

I/O Capacitance

D0~31

Symbol

C

IN1

C

IN2

C

I/O

Test Condition

V

IN

=0V

V

IN

=0V

V

I/O

=0V

typ

-

-

-

max

34

6

42

Unit

pF

pF

pF (8 bit mode)

Operating Modes

The Table below shows the logic inputs required to control the operating modes of each of the SRAMs on the

device.

Mode

Not Selected

Output Disable

Read

Write

1 = V

IH

,

0 = V

IL

,

X = Don't Care

CS

1

0

0

0

OE

X

1

0

X

WE

X

1

1

0

V

CC

Current

I

SB1

,I

SB2

I

CC

I

CC

I

CC

I/O Pin

High Z

High Z

D

OUT

D

IN

Reference Cycle

Power Down

Read cycle

Write Cycle

Note: CS above is accessed through CS1~4 and WE is accessed through WE1~4. For correct operation, CS1~ 4 and

WE1~4 must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation.

Low V

cc

Data Retention Characteristics - L Version Only

(T

A

=-55°C to +125

o

C)

Parameter

V

CC

for Data Retention

Data Retention Current

Symbol Test Condition

V

DR

I

CCDR

CS1~4

≥

V

CC

-0.2V

V

CC

= 3.0V, CS1~4

≥

V

CC

-0.2V,

0.2V

≥

V

IN

≥

V

CC

-0.2V

See Retention Waveform

See Retention Waveform

min

2.0

-

0

5

typ

-

-

-

-

max

3.6

28

-

-

Unit

V

mA

ns

ms

Chip Deselect to Data Retention t

CDR

Operation Recovery Time

t

R

AC Test Conditions

*Input pulse levels: 0.0V to 3.0V

*Input rise and fall times: 3 ns

*Input and Output timing reference levels: 1.5V

*V

cc

=3.3V±10%

*PUMA module is tested in 32 bit mode.

Output Load

I/O Pin

166

Ω

1.76V

30pF

3