PUMA2/67/77S4000/A-020/025/35
Issue4.3:December1999
Write Cycle No.2 Timing Waveform (5)
tWC
A0~A16
CS1~4
(4)
tCW
(6)
tAW
tWP(1)
tWR(2)
WE1~4
tAS(3)
tOH
tWHZ(3,9)
tOW
(8)
(7)
High-Z
D0~31out
D0~31in
tDW
tDH
High-Z
Low VCC Data Retention Timing Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
tCDR
tR
2.2V
2.2V
VDR
CS1~4 > Vcc-0.2V
CS1~4
0V
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low CS and a low WE.
(2) tWR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain
in a high impedance state.
(5) OE is continuously low. (OE=VIL)
(6) DOUT is in the same phase as written data of this write cycle.
(7) DOUT is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) tWHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
WE above refers to WE1~4 on the PUMA 2S4000, 67S4000A AND 77S4000A.
6
MOSAIC [ MOSAIC ]
