512K x 8 SRAM
MSM8512 - 020/025/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.0 : January 1999
Description
The MSM8512 is a 4Mbit monolithic SRAM organised
as 512K x 8 with access times from 20ns to 35ns
available. The device is available in two 32 pin ceramic
surface mount packages. The device has a low power
standby version which supports data retention mode
and is directly TTL compatible.
524,288 x 8 CMOS Static RAM
Features
Fast Access Times of 020/025/35 ns
High Density Packages.
Operating Power 950 mW (nom)
Standby Power
75 mW (nom) -L version
Low voltage data retention.
Completely Static Operation
Directly TTL compatible
May be processed in accordance with
MIL-STD-883C
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•
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All versions can be screened in accordance with MIL- •
•
STD-883C.
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Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D7
WE
OE
CS
X ADDRESS BUFFER
Pin Definition
D6
D5
D4
D3
GND
D2
ROW DECODER
4,194,304
BIT
MEMORY
ARRAY
D7
CS
A10
OE
A11
A9
A8
A13
WE
21
22
23
24
25
26
27
28
29
20 19 18 17 16 15 14
13
12
11
10
9
8
7
6
5
D0
A0
A1
A2
A3
A4
A5
A6
A7
J/ W
I/O
BUFFER
COLUMN I/O
COLUMN DECODER
Y ADDRESS BUFFER
A10
A11
A12
A13
A14
A15
A16
A17
A18
1
30 31 32
2 3 4
A17
VCC
A15
A18
A16
Package Details
Pin Count
32
32
Descripion
JLCC Package
LCC Package
Package Type
J
W
Pin Functions
A0~A18
Address Inputs
D0~7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
Power (+5V)
V
CC
GND
Ground
A14
A12
D1
MOSAIC [ MOSAIC ]
