MSM8128-70/85/10/12
Issue 4.5 : April 2001
Operating Modes
The table below shows the logic inputs required to control the MSM8128 SRAM.
Mode
CS1 CS2 OE WE
VCC Current
SB1,ISB2
ISB,ISB1
ICC
I/O Pin Reference Cycle
Not Selected
Not Selected
Output Disable
Read
1
X
0
0
0
X
0
1
1
1
X
X
1
X
X
1
1
0
I
High Z
High Z
High Z
DOUT
Power Down
Power Down
0
ICC
Read Cycle
Write Cycle
Write
X
ICC
DIN
1 = VIH,
0 = VIL,
X = Don't Care
Low Vcc Data Retention Characteristics - L Version Only (TA=-55°C to +125oC)
Parameter
Symbol Test Condition
VDR CS1 ≥ VCC-0.2V, CS2 ≥ VCC-0.2V or
0V ≤ CS2 ≤ 0.2V. VIN ≥ 0V
min
typ
max Unit
VCC for Data Retention
2.0
-
-
V
Data Retention Current
ICCDR VCC=3.0V,VIN ≥ 0V, CS1 ≥VCC-0.2V,
CS2 ≥ VCC-0.2V or 0V ≤ CS2 ≤ 0.2V.
-
0
5
-
-
-
660
µA
ns
Chip Deselect to Data Retention tCDR
Operation Recovery Time tR
See Retention Waveform
See Retention Waveform
-
-
ms
Notes (1) CS2 controls address buffer, WE buffer, CS1 buffer and OE buffer. If CS2 controls data retention mode,
Vin levels (WE,OE,CS1,I/O) can be in the high impedance state. If CS1 controls Data Retention mode,
CS2 must be ≥ VCC - 0.2V or 0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE,OE,I/O) can be in the
high impedance state.
AC Test Conditions
Output Load
I/O Pin
Ω
166
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* Vcc=5V±10%
1.76V
30pF
3
MOSAIC [ MOSAIC ]
