ISSUE 4.3 : November 1998
MSM8128X - 020/25/35
Write Cycle No.2 Timing Waveform
(5)
t
WC
A0~A16
t
CW
CS
(6)
(4)
t
AW
t
WP(1)
WE
t
WR(2)
t
AS(3)
t
WHZ(3,9)
t
OW
High-Z
t
DW
t
OH
(8)
(7)
D0~7out
t
DH
D0~7in
High-Z
Low V
CC
Data Retention Timing Waveform
Vcc
4.5V
DATA RETENTION MODE
4.5V
t
CDR
2.2V
t
R
2.2V
V
DR
CS1~4 > Vcc-0.2V
0V
CS1~4
AC Characteristics Notes
(1) A write occurs during the overlap (t
WP
) of a low CS and a low WE.
(2) t
WR
is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain
in a high impedance state.
(5) OE is continuously low. (OE=V
IL
)
(6) D
OUT
is in the same phase as written data of this write cycle.
(7) D
OUT
is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) t
WHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
6
MOSAIC [ MOSAIC ]
