MSM8128X - 020/25/35
ISSUE 4.3 : November 1998
Operating Modes
The table below shows the logic inputs required to control the MSM8128X SRAM.
Mode
Not Selected
Output Disable
Read
Write
CS
1
0
0
0
OE
X
1
0
X
WE
X
1
1
0
V
CC
Current
I
SB
,I
SB1
I
CC
I
CC
I
CC
I/O Pin
High Z
High Z
D
OUT
D
IN
Reference Cycle
Power Down
Read Cycle
Write Cycle
1 = V
IH
,
0 = V
IL
,
X = Don't Care
Low V
cc
Data Retention Characteristics - L Version Only
(T
A
=-55
O
C to +125
O
C)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retentiont
Operation Recovery Time
Symbol
V
DR
I
CCDR
t
CDR
t
R
Test Condition
CS≥V
CC
-0.2V
V
CC
=3.0V, CS≥V
CC
-0.2V,
0.2V≥V
IN
≥V
CC
-0.2V
See Retention Waveform
See Retention Waveform
min
2
-
-
-
typ
-
-
-
-
max
-
5
-
-
Unit
V
mA
ns
ms
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 3ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* V
cc
=5V±10%
Output Load
I/O Pin
166
Ω
1.76V
30pF
3
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