MFM8516 - 70/90/12/15
ISSUE 4.7 : NOVEMBER 1998
DATA PROTECTION
The MFM8516 is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its controls register architecture , alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power up
and power down transitions or system noise.
Low Vcc Write Inhibit
To avoid initiation of a write cycle during VCC power up and power down, a write cycle is locked out for
VCC<VLKO. When VCC<VLKO, the command register is disabled and all internal program/erase circuits are disa-
bled, and the device resets to the read mode. Subsequent writes will be ignored until the VCC>VLKO.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE, CS, WE will not initiate a write cycle
Logical Inhibit
Writing is inhibited by holding any one of OE=VIL, CS=VIH or WE=VIH. To initiate a write cycle CS and WE
must be logical zero while OE is a logical one.
Power Up Write Inhibit
Power-up of the device with WE = CS = VIL and OE = VIH will not accept commands on the rising edge of
WE. The internal state machine is automatically reset to the read mode on power-up.
Sector Protect
Sectors of the MFM8516 may be hardware protected at the users factory. The protection circuitry will disable
both program and erase functions for the protected sector(s). Requests to program or erase a protected sector
will be ignored by the device.
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Min
Typ
Max
Unit
Comments
Sector Erase Time
1
(Note 1)
8
15
sec
Excludes 00H programming
prior to erasure.
Chip Erase Time
120
1000
25
sec
µs
Excludes 00H programming
prior to erasure.
Byte Programming Time
Chip Programming Time
7
Excludes System-level overhead.
(Note 1)
3.6
sec
Excludes system-level overhead.
(Note 1) (Note 2)
Notes: (1) 25OC, 5V VCC, 10,000 cycles.
(2) The Embedded Algorithms allow for 2.5ms byte program time.
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