MFM8516 - 70/90/12/15
ISSUE 4.7 : NOVEMBER 1998
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
"unlock" write cycle. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of WE or CS, whichever happens later, while the data are latched on the rising edge
of WE or CS whichever happens first. The rising edge of WE or CS begins programming. Upon executing the
Embedded Program Algorithm Command sequence the system is not required to provide further controls or
timings. The device will automatically provide adequate internally generated program pulses and verify the
programmed cell margin. The automatic programming operation is completed when the data on D7 is equiva-
lent to data written to this bit (see Write Operations Status) at which time the device returns to the read mode
and addresses are no longer latched. Data Polling must be performed at the memory location which is being
programmed.
Programming is allowed in any address sequence and across sector boundaries.
Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock"write cycles. These are followed by writing
the "Set-up" command. Two more "unlock" write cycles are then followed by the sector erase command. The
sector address (any address location within the desired sector) is latched on the falling edge of WE, while the
command (data) is latched on the rising edge of WE. A time-out of 80µs from the rising edge of the last sector
erase command will initiate the sector erase command(s).
Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be
concurrently erased. The time between writes must be less than 80µs, otherwise the command will not be
accepted. It is recommended that processor interrupts be disabled during this time to guarantee this condition.
The interrupts can be-enabled after the last Sector Erase command is written. A time-out of 80µs from the
rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of
the WE occurs within the 80us time-out window the timer is reset. Any command other than Sector Erase or
Erase Suspend during this period and afterwards will reset the device to read mode, ignoring the previous
command string. Resetting the device after it has begun execution will result in the data of the operated
sectors being undefined. In that case, restart the erase on those sectors and allow them to complete. Loading
the sector erase buffer may be done in any sequence and with any number of sectors.
Sector erase doesn't require the user to program the device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors
the remaining unselected sectors are not affected. The system is not required to provide any controls or
timings during these operations.
The automatic sector erase begins after the 100µs time-out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the data on D7 is "1" ( see Written Operation Status
Section) at which time the device returns to read mode. Data polling must be preformed at an address within
any of the sectors being erased.
Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device automatically will program and verify the entire memory for an
all zero data pattern prior to electrical erase. The systems is not required to provide any controls or timings
during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on D7 is "1" (See Written Operation Section) at which time the device returns to read the mode.
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MOSAIC [ MOSAIC ]
