128K x 8 FLASH
MFM8126S - 70/90/12
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.2 : November 1998
General Description
The MFM8126 is a 1Mbit CMOS 5.0V only FLASH
memory arranged as 128K X 8.
Flash memory combines the functionality of
EEPROM with on board electrical Write/Erasure,
which reliably stores data even after 10,000 cycles.
The device incorporates Automatic Programming
and Erase functions, thus simplifying the external
control circuitry.
In addition, a Sector Erase function is available
which can erase one 16K block of data randomly
and more than one block simultaneously. The
MFM8126 also features hardware sector
protection, which enables both program and erase
operations in any of the 8 sectors.
Features
• Fast Access Time of 70 / 90 / 120ns.
• Operating Power Read
165mW (Max)
Program/Erase 275mW (Max)
Standby Power
5.5mW (Max)
• JEDEC standard package.
• Four package styles.
• Flexible Sector Erase Architecture - 16K byte sector
size, with hardware protection of any number of sectors.
• Single Byte Program of 14µs (typical), Sector Program /
Verify time of 0.3 sec. (typical).
• Device FLASH Erase / Verify of 3 seconds (typical).
• Erase/Write Cycle Endurance 10,000 (minimum)
• Extended endurance (E) option
• Can be screened in accordance with MIL-STD-883.
Block Diagram
D0-D7
Vcc
Vss
Erase Voltage
Generator
Input/Output
Buffers
Pin Definitions
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8 TOP VIEW
V,S
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
W
E
NC
A14
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
WE
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data
Latch
CS
OE
Embedded
Algorithms
STB
Timer
Package Details
Pin Count
Description
32
32
32
32
Package Type
TM
Pin Functions
A0-A16
D0-D7
CS
WE
OE
Vcc
GND
0.1" Vertical-in-line (VIL )
0.6" Dual-in-line (DIL)
Leadless Chip Carrier (LCC)
J Leaded Chip Carrier (JLCC)
V
S
W
J
D7
CS
A10
OE
A11
A9
A8
A13
A14
21
22
23
24
25
26
27
28
29
D1
D2
GND
D3
D4
D5
D6
13
12
11
10
9
8
7
6
5
A0-A16
L
a
t
c
h
X-Decoder
Cell Matrix
D0
A0
A1
A2
A3
A4
A5
A6
A7
Vcc Detector
A
d
d
r
Y-Decoder
Y-Gating
14
15
16
17
18
19
20
TOP VIEW
J,W
4
3
2
1
32
31
30
A12
A15
A16
NC
VCC
WE
NC
Address Inputs
Data Inputs/Outputs
Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
MOSAIC [ MOSAIC ]
