MFM8126S-70/90/12
ISSUE4.2:November1998
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may be
used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase cycle
has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is
completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional sector erase
commands. To insure the command has been accepted, the software should check the status of D3 prior to and
following each subsequent sector erase command. If D3 were high on the second status check, the command
may not have been accepted.
Data Protection
The MFM8126 is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets the
internal state machine in the Read mode. Also, with its controls register architecture , alteration of the memory
contents only occurs after successful completion of specific multi-bus cycle command sequences. The device
also incorporates several features to prevent inadvertent write cycles resulting from Vcc power up and power
down transitions or system noise.
Low V Write Inhibit
CC
To avoid initiation of a write cycle during VCC power up and power down, a write cycle is locked out for VCC less
than 3.2V (typically 3.7V). If VCC<VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to read mode. Subsequent writes will be ignored until the
VCC level is greater than VKLO. It is usually correct to prevent unintentional writes when VCC is above 3.2V.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE, CS, WE will not initiate a write cycle
Logical Inhibit
Writing is inhibited by holding any one of OE=VIL, CS=VIH or WE=VIH. To initiate a write cycle CS and WE
must be logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE=CS=VIL and OE=VIH will not accept commands on the rising edge of WE. The
internal state machine is automatically reset to the read mode on power-up.
Sector Protect
Sectors of the MFM8126 may be hardware protected at the users factory. The protection circuitry will disable
both program and erase functions for the protected sector(s). Requests to program or erase a protected sector
will be ignored by the device.
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MOSAIC [ MOSAIC ]
