ISSUE 4.2:November1998
MFM8126S-70/90/12
Auto Select Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target systems. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally a desired system design practice.
The device contains an autoselect operation to supplement traditional PROM programming methodology. The
operation is initiated by writing the autoselect command sequence into the command register. Following the
command write, a read cycle from address XXX0H retrieves the manufacture code of 01H. A read cycle from
addressXXX1Hreturnsthedevicecode20H. AreadcyclefromaddressXXX2Hreturnsinformationastowhich
sectors are protected. All manufacturer and device codes will exhibit odd parity with the MSB (D7) defined as the
parity bit.
To terminate the operation, it is necessary to write the read/reset command sequence into the register.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
"unlock" write cycle. These are followed by the program set-up command and data write cycles. The addresses
are latched on the falling edge of CS or WE (whichever last), the data is latched on the rising edge of CS or WE
(whicheverfirst), andthenprogrammingbegins. UponexecutingtheEmbeddedProgramAlgorithmCommand
sequence the system is not required to provide further controls or timings. The device will automatically provide
adequateinternallygeneratedprogrampulsesandverifytheprogrammedcellmargin. Theautomatic
programming operation is completed when the data on D7 is equivalent to data written to this bit (see write
Operations Status) at which time the device returns to read mode and addresses are no longer latched. Data
Polling must be performed at the memory location which is being programmed.
Programming is allowed in any address sequence and across sector boundaries. Beware that data "0" cannot
be programmed back to a "1". Attempting to do so will hang up the device, or result in an apparent success
according to the data polling algorithm. However, a read from Read/Reset Mode will show data is still "0". Only
an erase operation can convert "0"s to "1"s.
ChipErase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are then followed by the chip erase command.
Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device automatically will program and verify the entire memory for an all zero
data pattern prior to electrical erase. The systems is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on D7 is "1" (See Written Operation Section) at which time the device returns to read the mode.
14
MOSAIC [ MOSAIC ]
