3 3 WINDOW
LINE N 1
LINE N
LINE N 1
C4
C8
C0
C5
C9
C1
C6
C10
C2
VIDEO
LINE N 2
FIELD
DELAY
IP7:0
ODD
FIELD
1024
N 1
1024
L7:0
1024
1024
N 1
4 4
OR
8 4
N
ARRAY
Output is shifted
by 1 line in
every field
5 5 WINDOW
LINE N 2
LINE N 1
LINE N
LINE N 1
LINE N 2
C48
C8
C40
C0
C32
C49
C9
C41
C1
C33
C50
C10
C42
C2
C34
C51
C11
C43
C3
C35
C52
C12
FIELD
DELAY
IP7:0
ODD
FIELD
512
N 1
512
512
512
VIDEO
LINE N 2
L7:0
DELAY
BYPASSED
REG B BIT 7 SET
512
N 2
512
512
512
N
N 2
N 1
C44
C4
C36
8 8
ARRAY
Output is shifted
by 1 line in
every field
8 8 WINDOW
LINE N 3
LINE N 2
LINE N 1
LINE N
LINE N 1
LINE N 2
LINE N 3
LINE N 4
C24
C56
C16
C48
C8
C40
C0
C32
C25
C57
C17
C49
C9
C41
C1
C33
C26
C58
C18
C50
C10
C42
C2
C34
C27
C59
C19
C51
C11
C43
C3
C35
C28
C60
C20
C52
C12
C44
C4
C36
C29
C61
C21
C53
C13
C45
C5
C37
C30
C62
C22
C54
C14
C46
C6
C38
C31
C63
C23
C55
C15
C47
C7
C39
FIELD
DELAY
IP7:0
ODD
FIELD
512
N 3
512
512
512
VIDEO
LINE N 4
L7:0
DELAY
BYPASSED
REG B BIT 7 SET
512
N 4
512 N 2
512
N
N 1
N 1
N 3
8 8
ARRAY
Output is shifted
by 2 lines in
every field
512 N 2
Fig. 5 Line delay allocations in SINGLE device interlaced systems
8
MITEL [ MITEL NETWORKS CORPORATION ]
