Switching Characteristics, operational timings
Value
Characteristic
Symbol
Units
Conditions
Min. Max.
tCL
tCH
CLK low time
25
10
25
10
10
0
21
20
10
15
15
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
32-bit multiplexed output
16-bit output
32-bit multiplexed output
16-bit output
CLK high time
tDSU
tDH
tRD
Data in setup time
Data in hold time
CLK rising to output delay
L7:0 output delay
HRES low setup time
Output enable time
Output disable time
X15:0 Expansion setup time
X15:0 Expansion hold time
Increase to 24ns for DELOP output
tLD
tRSU
tDLZ
tDHZ
tXSU
tXDH
Measured with a 15kWseries resistor and 30pF
load capacitance
7
tCH
tCL
CLK
tLD
VALID
L7:0 LINE STORE OUTPUTS
tRSU
HRES
OEN
tRD
tDHZ
HIGH Z (D15:0 ONLY)
tDLZ
DATA AND FLAG OUTPUTS
PIXEL DATA IN
tDSU
tDH
VALID
tXSU
tXDH
tXSU
tXDH
VALID
VALID
VALID
X15:0 DATA IN
Fig. 12 Operational timing
20