Gain Control Block
This block is provided as an aid to locating the bits of interest
in the 32-bit internal result. The magnitude of the largest convolved
output will depend on the size of the window, and the coefficient
values used. The function of the gain control block is then to
produce an output, which is accurate to 16 bits, and which is
aligned to the most significant end of this 32-bit word. The sixteen
most significant bits of the word are available on D15:0 and the
largest number need only have one sign bit if the gain control is
correctly adjusted.
Fig. 6 indicates the mechanism employed with the required
function implemented in two steps. Two mode control bits,
register C, bits 5:4, allow one of four 20 bit fields to be selected
from the final 32-bit value. These four fields are positioned with
the first at the most significant end, and then at four bit
displacements down to the least significant end.
By setting an enabling bit, register C, bit 0, the field selection
can optionally be done automatically. This feature should only be
used in the real time operating mode, when HRES defines video
lines. Internal logic examines the most significant 13, 9, or 5 bits
from the 32-bit result, and makes a field selection dependent on
which group does not contain identical sign bits. If less than five
sign bits are obtained, the logic will select the field containing the
most significant 20 bits. The selection is indicated by F1:0.
The automatic field selection is particularly useful when a
fixed scene is being processed. The selection is reset when any
internal register is updated (i.e.
PROG
has been low) and is then
held high for ten further occurrences of the HRES input. This
allows the internal multiplier/accumulator array to be completely
flushed before a field selection is made. As convolver outputs of
greater magnitude are produced the field selection logic will
respond by selecting a more significant field. The most significant
field found necessary remains selected until
PROG
again goes
low. Even if the automatic field selection is not enabled, F1:0 will
still indicate which field would have been selected. These are
coded in the same way as register C, bits 5:4.
Having chosen a field, either manually or automatically, it
is then multiplied by a 4-bit unsigned integer. This is contained
within the user-programmed gain control register, and the
multiplication will produce a 24-bit result . The middle 16 bits
of this result contain the required output bits. The gain control
multiplier can overflow in to the unused most significant four
bits if the parameters are chosen wrongly. This condition is
flagged by pin OVR.
By setting appropriate mode control bits, further manipulation
of the gain control output is possible. One option, register C, bits
FROM EXPANSION ADDER
7:6 = 11, allows all negative outputs to be forced to zero, and at
the same time positive gain control overflows will saturate at the
maximum positive number. Register C, bits 7:6 = 10 will saturate
positive and negative overflows at their respective maximum
values, but otherwise leaves them unchanged. Occasional over-
flows can be tolerated in some systems, and this option prevents
any gross errors.
Expansion
Multiple devices can be connected in cascade in order to
obtain window sizes larger than those provided by a single
PDSP16488A. This requires an additional adder in each device
which is fed from expansion data inputs. This adder is not used
by a Single device or the first device in a cascaded system, and
is enabled or disabled by register B, bit 4.
The first device in the cascaded system must be designated
as a Master device by
MASTER
tying low. Its expansion input
bus is then used as the source of data for the coefficient and
control registers in all devices in the system.
In order to reduce the pin count required for 32-bit buses, both
expansion in and data out are time-multiplexed with the phases
of the pixel clock. When the clock is high the least significant half
will be valid, and when the clock is low the most significant half will
be valid.
In practice this multiplexing is only possible with pixel clocks
up to 20MHz. Above these frequencies the multiplexing must be
inhibited by setting register A, bit 7. The intermediate data
accuracy will then be reduced, since only the lower 16 bits of the
internal 32-bit intermediate sum are available on the D15:0 output
pins. In such systems the coefficients must be scaled down in
order to keep the intermediate and final results down to 16 bits.
The final device should not use the gain control block but instead
should simply output the non-multiplexed 16-bit result. The OVR
flag and pixel saturation options will not be available.
Pixel Input and Output Delays
In a real time system, when line delays are referenced to
video sync pulses present on the HRES input, the first pixel from
the last line delay does not appear on the L7:0 pins until the fifth
active pixel clock edge after HRES has gone low. This is
illustrated in Fig. 8. In a vertically expanded system, this output
provides the input to the first line delays in the vertically displaced
devices. The internal logic is thus designed to always expect this
five clock delay. Compensation must thus be applied to the
devices which are directly connected to the video source, such
that the first pixel is not valid until the fifth clock rising edge.
For this reason the PDSP16488A contains an optional four
clock pipeline delay on each of the pixel data inputs, as shown in
Fig. 7. When the delay is used the first pixel in a video line must
be available on the input pins after the first pixel clock edge. This
would be so if the device were connected to an A-D converter,
since that would introduce a one pixel pipeline delay. If the system
introduces any further external pipeline delays, then the internal
delay should be bypassed, and the user should ensure that the
first pixel is valid after the fifth clock edge.
The use of this four clock delay is controlled by register B,
bit 3. This delay is in addition to the delays which are provided to
support expansion in both the X and Y directions, and are
controlled by register D, bits 3:2. Both delays are in fact simply
added together in the device, but are separately defined since
they add delays for different system reasons.
AUTOMATIC
FIELD SELECT
F1:0
32 BITS
MSB
20 12
4 20 8
8 20 4
12 20
LSB
D15:0
MUX
20
24
4
16
4
16
SATURATE
LOGIC
4
GAIN CONTROL
REGISTER
Fig. 6 Gain control block
9
MITEL [ MITEL NETWORKS CORPORATION ]
