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PDSP16488ACBR 参数 Datasheet PDF下载

PDSP16488ACBR图片预览
型号: PDSP16488ACBR
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片的二维卷积器与积分行延迟 [Single Chip 2D Convolver with Integral Line Delays]
分类和应用:
文件页数/大小: 33 页 / 414 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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INPUT
0
REG B3 = 1
DELAYS
PDSP16488A
0
REG B3 = 1
DELAYS
Nth PDSP16488A IN THE ROW
0
DELAY = 0, DEFINED BY REG D3:2 = 00
DELAYS
WIDTH = S
LINE
DELAYS
ZERO
4 CLOCK
DELAYS
0
DELAY = 0, DEFINED BY REG D3:2 = 00
DELAYS
WIDTH = S
LINE
DELAYS
Σ
0
DELAYS
REG D0 = 0
+
4 CLOCK
DELAY
Σ
0/4
DELAYS
REG D0 = 0 IF S = 4,
OR REG D0 = 1 IF S = 8
+
4 CLOCK
DELAY
0
REG B3 = 0
DELAYS
PDSP16488A
0
REG B3 = 1
DELAYS
Nth PDSP16488A IN THE ROW
D
D = 4 S(N 1) DEFINED BY REG D3:2
DELAYS
WIDTH = S
LINE
DELAYS
D
D = 4 S(N 1) DEFINED BY REG D3:2
DELAYS
WIDTH = S
LINE
DELAYS
Σ
0
DELAYS
REG D0 = 0
+
4 CLOCK
DELAY
Σ
0/4
DELAYS
REG D0 = 0 IF S = 4,
OR REG D0 = 1 IF S = 8
+
4 CLOCK
DELAY
4 CLOCK
DELAYS
0
REG B3 = 0
DELAYS
PDSP16488A
0
REG B3 = 1
DELAYS
Nth PDSP16488A IN THE ROW
D
D = 4 S(N 1) DEFINED BY REG D3:2
DELAYS
WIDTH = S
LINE
DELAYS
D
D = 4 S(N 1) DEFINED BY REG D3:2
DELAYS
WIDTH = S
LINE
DELAYS
Σ
0
DELAYS
REG D0 = 0
+
4 CLOCK
DELAY
Σ
0/4
DELAYS
REG D0 = 0 IF S = 4,
OR REG D0 = 1 IF S = 8
+
4 CLOCK
DELAY
OUTPUT
Fig. 7 Multi-device delay paths
Delay Compensation for Large Windows
A large window is composed of several partial windows each of
which is implemented in an individual device. If necessary the partial
window must be padded with zero coefficients to become one of the
standard sizes. When constructing a large window it is necessary to
delay the expansion data inputs in order to compensate for growth
in the horizontal direction. Delays in the partial sums are also
necessary to compensate for the total pipeline delay needed to
produce the previous complete horizontal stripe.
Within each device in a horizontal stripe, apart from the first,
the expansion input must be delayed by the width of the partial
window, before it is added to the internal sum. Since partial
windows can only be 4 or 8 pixels wide, a delay of 4 or 8 pixel
clocks is needed. There is, however, an in-built delay of 4 pixels
in the inter device connection, and the PDSP16488A thus only
needs an option to delay the expansion input by an additional four
pixels.
10