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PDSP16318MC 参数 Datasheet PDF下载

PDSP16318MC图片预览
型号: PDSP16318MC
PDF下载: 下载PDF文件 查看货源
内容描述: [PDSP16256GC1R]
分类和应用: 光电二极管
文件页数/大小: 8 页 / 92 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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PDSP16318/16318A  
ELECTRICAL CHARACTERISTICS  
Test conditions (unless otherwise stated):  
T
amb (Commercial) = 0°C to +70°C, VCC = 5.0V ± 5%, GND = 0V  
Tamb (Industrial) =-40°C to +85°C, VCC = 5.0V ± 10%, GND = 0V  
Tamb (Military) =-55°C to +125°C, VCC = 5.0V ± 10%, GND = 0V  
STATIC CHARACTERISTICS  
Value  
Characteristic  
Symbol  
Units  
Conditions  
Min.  
Typ.  
Max.  
Output high voltage  
Output low voltage  
Input high voltage  
Input low voltage  
Input leakage current  
Output leakage current  
Output SC current  
Input capacitance  
VOH  
VOL  
VIH  
VIL  
IIL  
loz  
IOS  
CIN  
2.4  
-
3.5  
-
-10  
-50  
20  
-
-
V
V
V
IOH = 3.2mA  
lOL=-3.2mA  
0.4  
-
0.5  
+10  
+50  
200  
-
V
µA  
µA  
mA  
pF  
GND < VIN<VCC  
GND <VOUT < VCC  
Vcc = Max  
-
-
9
SWITCHING CHARACTERISTICS  
Characteristic  
Value  
Industrial  
Value  
Military  
Units  
Conditions  
PDSP16318A PDSP16318  
Min.  
Max.  
Min.  
Max.  
Clock period  
Clock High Time  
Clock Low Time  
A15:0, B15:0 setup to clock rising edge  
A15:0, B15:0 hold after clock rising edge  
MS, S2:0, ASI setup to clock rising edge  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100  
20  
20  
8
2
10  
8
-
-
-
-
-
-
-
-
50  
15  
15  
5
2
10  
5
-
-
-
-
-
-
-
-
DEL, ASR, CLR setup to clock rising edge  
DEL, ASR, CLR, MS, S2:0, ASI hold after  
clock rising edge  
2
2
ns  
ns  
ns  
ns  
ns  
ns  
mA  
2
8
5
-
-
-
-
-
2
8
5
-
-
-
-
-
CEA, CEB setup to clock falling edge  
CEA, CEB hold after clock rising edge  
Clock rising edge to OVR, C15:0, D15:0  
2 x LSTTL + 20pF  
2 x LSTTL + 20pF  
2 x LSTTL + 20pF  
2 x LSTTL + 20pF  
VCC = max,  
40  
40  
40  
40  
70  
30  
30  
30  
30  
110  
OEC/OED low to C15:0/D15:0 high data valid  
OEC/OED low to C15:0/D15:0 low data valid  
OEC/OED high to C15:0/D15:0 high impedance  
Vcc current  
-
-
TTL input levels  
Outputs unloaded,  
fCLK = max  
Vcc current  
mA  
VCC = max,  
-
30  
-
60  
CMOS input levels  
Outputs unloaded,  
fCLK = max  
NOTES  
1. LSTTL is equivalent to IOH = 20 microamps, IOL = -0.4mA  
2. Current is defined as negative into the device  
3. CMOS input levels are defined as:  
VIL = 0.5  
VIH = VDD - 0.5  
6