PDSP16318/16318A
Function GC pin Function GC pin
GC pin Function GC pin
Function
C7
C6
C5
C4
C3
C2
C1
C0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
5
D7
D8
D9
6
7
8
9
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
CLK
D10
GND
VCC
D11
D12
D13
D14
D15
C15
C14
C13
C12
VCC
GND
C11
C10
C9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
OED
OEC
S2
S1
S0
MS
ASI1
ASI0
CEB
OVR
D0
D1
D2
D3
D4
D5
D6
CEA
B15
B14
B13
B12
B11
DEL
CLR
ASR1
ASR0
A0
C8
Device Pinout for ceramic QFP (GC100)
DEL Delay Mux Control
ASR or ASI
ALU Function
ASX1 ASX0
0
1
A port input
Delayed A port input
0
0
1
1
0
1
0
1
A + B
A
A - B
B - A
MS Real and Imag' Mux Control
0
1
B port input/Del mux output
C accumulator/D accumualtor
S2:0
S2 S1 S0 19
Adder result
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
15
14
15
13
14
15
12
13
14
15
11
12
13
14
15
10
11
12
13
14
15
9
8
9
7
8
9
10
11
12
13
14
6
7
8
5
6
7
8
9
10
11
12
4
5
6
7
8
9
10
11
3
4
5
6
7
8
9
10
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
10
11
12
13
14
15
0
1
2
3
4
5
6
10
11
12
13
14
15
0
1
2
3
4
5
9
0
1
2
3
4
10
11
12
13
0
1
2
3
NOTE
This table shows the portion of the adder result passed to the D15:0 and C15:0 outputs. Where fewer than 16 adder bits are selected
the output data is padded with zeros.
4
MITEL [ MITEL NETWORKS CORPORATION ]
