PDSP16116
tCLK
CLK
tCLKH
tCLKL
tCP
VALID DATA
VALID DATA
OUTPUT P PORTS
tCSFTA
tCSFTA
OUTPUT SFTA1:0
tDS
tDH
INPUT DATA X AND Y
tCES
tCEH
INPUT CONTROLS CEX AND CEY
tCONS
tCONH
INPUT CONTROLS CONX AND CONY
INPUT CONTROL WTB1:0
tWS
tWH
Fig. 9 Normal mode timing
OER AND OEI
tOPLZ
tOPZL
tOPZH
tOPHZ
HIGH Z
HIGH Z
HIGH Z
OUTPUT P PORTS
Fig. 10 Output tristate timing
Test
Waveform measurement level
Delay from
output high
to output
V
H
0·5V
V
V
= 0V
T
high Z (t
)
OPHZ
Delay from
output low
to output
= V
DD
T
1·5k
0·5V
0·5V
V
VT
DUT
30p
L
high Z (t
)
OPLZ
Delay from
1·5V
output high Z
to output low
Three state delay measurement load
(t
OPZL
)
Delay from
output high Z
to output high
0·5V
1·5V
(t
)
OPZH
VH is the voltage reached when the output is driven high
V is the voltage reached when the output is driven low
L
Fig. 11 Three state delay measurement
12
MITEL [ MITEL NETWORKS CORPORATION ]
