PDSP1601 MC
ELECTRICAL CHARACTERISTICS
Operating Conditions (unless otherwise stated)
TAMB (Military) = -55°C to +125°C, VCC = 5.0V±10%, Ground = 0V
Static Characteristics
Symbol
Value
Typ.
Conditions
Units
Sub
group
Characteristic
Min.
2.4
Max.
VOH
VOL
VIH
VIL
VIH
VIL
IIL
ICC
IOZ
ISC
IOH = 8mA
V
V
V
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
* Output high voltage
* Output low voltage
* Input high voltage
* Input low voltage
I
OL = -8mA
0.4
0.8
2.5
CLOCK, OE
CLOCK, OE
GND < VIN < VCC
Tamb = -40°C to +85°C
GND < VOUT < VCC
VCC = Max
Vdd -1
-10
0.5
+10
60
+50
80
V
µA
mA
µA
mA
pF
* Input leakage current
* Vcc current
* Output leakage current
† Output S/C current
† Input capacitance
-50
12
CIN
5
Switching Characteristics
Value
PDSP1601
Characteristics
Units
Sub
Conditions
group
Min.
Max.
5
5
5
30
40
40
2 x LSTTL + 20pF
1 x LSTTL + 5pF
1 x LSTTL + 5pF
40
100
100
†
†
†
†
†
†
†
†
CLK rising edge to C-PORT
CLK rising edge to CO
CLK rising edge to BFP
Setup CEA or CEB to CLK rising edge
Hold CEA or CEB to CLK rising edge
Setup A or B port inputs to CLK rising edge
Hold A or B port inputs to CLK rising edge
ns
ns
ns
ns
ns
ns
ns
ns
0
0
Setup MSA0-1, MSB, MSS, MSC, RA2-0, RS0-2, IA0-4,
IS0-3, to CLK rising edge
0
3
0
†
†
†
†
†
†
†
†
†
†
†
*
Hold RS0-2, IA0-4 to CLK rising edge
Hold IS0-3 to CLK rising edge
Hold MSA0-1, MSB, MSS, MSC, RA0-2 to CLK rising edge
Setup SV to CLK rising edge
Hold SV to CLK rising edge
CLK rising edge to SV
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
5
Input mode
Input mode
3
100
40
40
40
40
20pF load, SV O P mode
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
2 x LSTTL + 20pF
OE
OE
OE
OE
C-PORT
C-PORT
C-PORT Z
C-PORT Z
Z
Z
200
100
40
Clock period (ALU & Barrel Shifter, serial mode)
Clock period (ALU & Barrel Shifter, parallel mode)
Clock high time
ns 9, 10, 11
ns
sn
†
†
40
Clock low time
All parameter marked * are tested during production.
Parameters marked † are guaranteed by design and characterisation
14
MITEL [ MITEL NETWORKS CORPORATION ]
