NWK933
General
The following is the register set that is implemented in the NWK933 device:
The interface to these registers is via the MDC and MDIO signals. The address of the NWK933 is specified by
the PA<4:0> static inputs The MD command is issued by the controller and can be read or write:
command preamble
READ
WRITE
32 bits of 1
32 bits of 1
start data
01
01
op code
10
01
phy address reg number
5 bits
5 bits
5 bits
5 bits
TA
Z0
10
Data
16 bit from phy
16 bit from MAC
SC = Self clear
RO = read only
RW = read or write
LL = latch low until register read
LH = latch high until register read
Register Set
reg 0 - control register
Bit
0.15
0.14
0.13
0.12
0.11
0.10
0.9
0.8
0.7
0.6:0
Bit name
Reset
Loopback
Speed
selection
ANEG
enable
Power down
Isolation
Restart
ANEG
Duplex
selection
Collision
test
Reserved
Description
1 = PHY reset
0 = Normal operation
1 = Loopback mode active
0 = Normal operation
1 = 100 Mbps
0 = 10 Mbps
1 = Enable ANEG process
0 = Disable ANEG process
1 = Power down active
0 = Normal operation
1 = isolation in process
0 = Normal operation
1 = Restart the ANEG process
0 = Normal operation
1= Full Duplex mode
0 = Half duplex mode
1 = Collision test active
0 = Normal operation
Write as 0 ignore on read.
Default
0
0
1
1
0
0
0
1
0
R/W
RW
SC
RW
RW
RW
RW
RW
RW
SC
RW
RW
9
MITEL [ MITEL NETWORKS CORPORATION ]
