Advance Information
Dout, on the rising edge of BCL during the time slot
defined by the STB input. Dout is tri-stated at all
times when STB is not true. If STB is valid, then quiet
code will be transmitted on Dout during the valid
strobe period. There is no frame delay through the
PCM serial circuit for synchronous operation.
For asynchronous operation Dout and Din are as
defined for synchronous operation except that the
allowed output jitter on Dout is larger. This is due to
the resynchronization circuitry activity and will not
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the PCM serial circuit for
asynchronous operation. Refer to the specifications
of Figures 5 & 6 for both synchronous and
asynchronous SSI timing.
PWRST
While the MT91L62 is held in PWRST no device
control or functionality is possible.
MT91L62
Applications
Figure 4 shows an application of the MT91L62 in a
line card.
0.1
µF
VBias
Input from Subscriber
Line Interface
0.1
µF
0.1
µF
100k
100k
1k
100k
1k
100k
1k
100k CS0
1k
100k CS1
1k
100k
1k
CS2
Din
Dout
Timing
Frame Pulse
Block
Clock
A/µ
RxMUTE
TxMUTE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
+3V
Output to Subscriber
Line Interface
+3V
MT91L62
Figure 4 - Line Card Application
7-177
MITEL [ MITEL NETWORKS CORPORATION ]
