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MT91L62AN 参数 Datasheet PDF下载

MT91L62AN图片预览
型号: MT91L62AN
PDF下载: 下载PDF文件 查看货源
内容描述: ISO2 - CMOS 3伏单轨编解码器 [ISO2-CMOS 3 Volt Single Rail Codec]
分类和应用: 解码器编解码器
文件页数/大小: 17 页 / 81 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT91L62
External
Clock Bit
Rate
(kHz)
128
256
512
1536
2048
4096
Advance Information
In SSI mode the MT91L62 supports only B-Channel
operation. Hence, in SSI mode transmit and receive
B-Channel data are always in the channel defined by
the STB input.
The data strobe input STB determines the 8-bit
timeslot used by the device for both transmit and
receive data. This is an active high signal with an 8
kHz repetition rate.
SSI operation is separated into two categories based
upon the data rate of the available bit clock. If the bit
clock is 512 kHz or greater then it is used directly by
the
internal
MT91L62
functions
allowing
synchronous operation. If the available bit clock is
128 kHz or 256 kHz, then a 4096 kHz master clock is
required to derive clocks for the internal MT91L62
functions.
Applications where Bit Clock (BCL) is below 512 kHz
are designated as asynchronous. The MT91L62 will
re-align its internal clocks to allow operation when
the external master and bit clocks are asynchronous.
Control pins CSL2, CSL1 and CSL0 are used to
program the bit rates.
For synchronous operation, data is sampled from
Din, on the falling edge of BCL during the time slot
defined by the STB input. Data is made available, on
CSL
2
CSL
1
CSL
0
CLOCKin
(kHz)
4096
4096
512
1536
2048
4096
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
Table 2: Bit Clock Rate Selection
TxMute pin is high. When either of these pins are low
their respective paths function normally. The -Zero
entry of Table 1 is used for the quiet code definition.
SSI Mode
The SSI BUS consists of input and output serial data
streams named Din and Dout respectively, a Clock
input signal (CLOCKin), and a framing strobe input
(STB). A 4.096 MHz master clock is also required for
SSI operation if the bit clock is less than 512 kHz.
The timing requirements for SSI are shown in
Figures 5 & 6.
Serial
Port
Filter/Codec and Analog Interface
Default Bypass
Aout +
Decoder
Receive
Filter Gain
0 dB
0 dB
Receiver
Driver
20kΩ
PCM
D
in
Aout-
PCM
D
out
Transmit Gain
Encoder
6 dB
AIN+
AIN-
Analog
Input
Internal To Device
External To Device
Figure 3 - Audio Gain Partitioning
7-176