MT91L60/61
Advance Information
Tj
70%
STB
30%
tdda2
tdha1
tdda1
70%
Dout
Bit 1
Bit 2
Bit 3
30%
TDATA
TDATA1
tho
tsu
70%
Din
D2
D3
D1
30%
T
DATA/2
TDATA
TDATA
NOTE: Levels refer to % VDD (CMOS I/O)
Figure 13 - SSI Asynchronous Timing Diagram
AC Electrical Characteristics† - Microport Timing (see Figure 14)
‡
Characteristics
Input data setup
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
5
6
7
8
9
tIDS
tIDH
100
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input data hold
Output data delay
Serial clock period
SCLK pulse width high
SCLK pulse width low
CS setup-Intel
tODD
tCYC
tCH
120
CL = 50pF, RL = 1K *
500
250
250
200
100
100
1000
500
tCL
500
tCSSI
tCSSM
tCSH
tOHZ
CS setup-Motorola
CS hold
10 CS to output high impedance
120
CL = 50pF, RL = 1K
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Note: All conditions → data-data, data-HiZ, HiZ-data.
26
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