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MT91L61AE 参数 Datasheet PDF下载

MT91L61AE图片预览
型号: MT91L61AE
PDF下载: 下载PDF文件 查看货源
内容描述: ISO2 - CMOS 3伏多功能的编解码器( MFC) [ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)]
分类和应用: 解码器编解码器电信集成电路光电二极管
文件页数/大小: 32 页 / 148 K
品牌: MITEL [ MITEL NETWORKS CORPORATION ]
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MT91L60/61  
Advance Information  
AC Electrical Characteristics- SSI BUS Synchronous Timing (see Figure 12)  
Characteristics  
BCL Clock Period  
Sym  
Min  
Typ  
Max Units  
Test Conditions  
1
2
3
4
5
6
7
8
9
tBCL  
tBCLH  
tBCLL  
tR/tF  
244  
115  
1953  
ns BCL=4096 kHz to 512 kHz  
ns BCL=4096 kHz  
ns BCL=4096 kHz  
ns Note 1  
BCL Pulse Width High  
122  
122  
BCL Pulse Width Low  
BCL Rise/Fall Time  
20  
8 x tBCL  
8 x tBCL  
Strobe Pulse Width  
tENW  
tENWD  
tSSS  
ns Note 1  
Delayed Strobe Pulse Width  
Strobe setup time before BCL falling  
Strobe hold time after BCL falling  
ns Note 1  
tBCL-80  
tBCL-80  
55  
70  
80  
ns  
tSSH  
ns  
Delayed Strobe Pulse delay after BCL tDSTBR  
rising  
ns Note 1  
10 Delayed Strobe Pulse hold time after  
BCL rising  
tDSTBF  
tDOZL  
tDOZH  
tDOLZ  
tDOHZ  
tDD  
55  
55  
55  
90  
90  
80  
ns Note 1  
11 Dout High Impedance to Active Low  
from Strobe rising  
ns CL=50 pF, RL=1K  
ns CL=50 pF, RL=1K  
ns CL=50 pF, RL=1K  
ns CL=50 pF, RL=1K  
ns CL=50 pF, RL=1K  
12 Dout High Impedance to Active High  
from Strobe rising  
13 Dout Active Low to High Impedance  
from Strobe falling  
14 Dout Active High to High Impedance  
from Strobe falling  
15 Dout Delay (high and low) from BCL  
rising  
16 Din Setup time before BCL falling  
17 Din Hold Time from BCL falling  
tDIS  
tDIH  
10  
50  
ns  
ns  
† Timing is over recommended temperature range & recommended power supply voltages.  
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.  
Note 1: Not production tested, guaranteed by design.  
24  
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