Advance Information
For synchronous operation, data is sampled from
Din, on the falling edge of BCL during the time slot
defined by the STB input. Data is made available, on
Dout, on the rising edge of BCL during the time slot
defined by the STB input. Dout is tri-stated at all
times when STB is not true. If STB is valid, then quiet
code will be transmitted on Dout during the valid
strobe period. There is no frame delay through the
PCM serial circuit for synchronous operation.
For asynchronous operation Dout and Din are as
defined for synchronous operation except that the
allowed output jitter on Dout is larger. This is due to
the resynchronization circuitry activity and will not
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the PCM serial circuit for
asynchronous operation. Refer to the specifications
of Figures 5 & 6 for both synchronous and
asynchronous SSI timing.
PWRST
While the MT9162 is held in PWRST no device
control or functionality is possible.
VBias
1
µF
0.1
µF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
MT9162
Applications
Figure 4 shows the MT9162 in a line card
application.
0.1
µF
(
Typical External Gain
AV= 5-10
)
Input from Subscriber
Line Interface
+5V
100k
100k
1k
100k
1k
100k
1k
100k CS0
1k
100k CS1
1k
100k
1k
CS2
A/µ
RxMUTE
TxMUTE
Out to Subscriber Line
Interface
+5V
MT9162
DC to DC
Converter
+5V
Din
Lin
MT8972
Dout
Frame Pulse
From Digital
Phone
Twisted Pair
Z
T
DNIC
Lout
Clock
Figure 4 - Line Card Application
7-165
MITEL [ MITEL NETWORKS CORPORATION ]
