MT9162
Advance Information
VBias
VRef
PWRST
IC
A/µ
RXMUTE
TXMUTE
CSL0
CSL1
CSL2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AIN+
AIN-
VSS
AOUT +
AOUT -
VDD
CLOCKin
STB
Din
Dout
20 PIN PDIP/SOIC/SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
Name
V
Bias
V
Ref
Description
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external amplifiers.
Connect 0.1
µ
F capacitor to V
SS
. Connect 1
µF
capacitor to Vref.
Reference Voltage for Codec (Output).
Nominally [(V
DD
/2)-1.9] volts. Used internally.
Connect 0.1
µ
F capacitor to V
SS
. Connect 1
µF
capacitor to VBias
Internal Connection.
Tie externally to V
SS
for normal operation.
A/µ Law Selection.
CMOS level compatable input pin governs the companding law used by
the device. A-law selected when pin tied to V
DD
or
µ-law
selected when pin tied to V
SS
.
PWRST
Power-up Reset.
Resets internal state of device via Schmitt Trigger input (active low).
IC
A/µ
RXMute
Receive Mute.
When 1, the transmit PCM is forced to negative zero code. When 0, normal
operation. CMOS level compatible.
TXMute
Transmit Mute.
When 1, the transmit PCM is forced to negative zero code. When 0, normal
operation. CMOS level compatible.
CSL0
CSL1
CSL2
D
out
Clock Speed Select.
These pins are used to program the speed of the SSI mode as well as
the conversion rate between the externally supplied MCL clock and the 512 kHz clock required
by the filter/codec. Refer to Table 2 for details. CMOS level compatible.
Data Output.
A tri-state digital output for 8-bit wide channel data being sent to the Layer 1
device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot
defined by STB.
Data Input.
A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the
falling edge of BCL during the timeslot defined by STB. CMOS level compatible.
Data Strobe.
This input determines the 8-bit timeslot used by the device for both transmit and
receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatible.
12
13
14
D
in
STB
CLOCKin
Clock (Input).
The clock provided to this input pin is used by the internal device functions.
Connect bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin
when the bit clock is 128 kHz or 256 kHz. CMOS level compatible.
V
DD
AOUT-
Positive Power Supply.
Nominally 5 volts.
Inverting Analog Output.
(balanced).
15
16
17
18
19
20
7-162
AOUT+
Non-Inverting Analog Output.
(balanced).
V
SS
Ain-
Ain+
Ground.
Nominally 0 volts.
Inverting Analog Input.
No external anti-aliasing is required.
Non-Inverting Analog Input.
Non-inverting input. No external anti-aliasing is required.
MITEL [ MITEL NETWORKS CORPORATION ]
