MT9125
Preliminary Information
24 PIN PDIP
MCLK
F0i
C2o
DSTo
DSTi
BCLK
VSS
ENB2
ENB1
MS1
MS2
MS3
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
ENS
EN2
EN1
ADPCMo
ADPCMi
ENA
VDD
IC
PWRDN
FORMAT
A/µ
MS4
28 PIN PLCC
Figure 2 - Pin Connections
Pin Description
Pin #
DIP
PLCC
Name
MCLK
1
2
Master Clock input. This 4.096 MHz clock is used as an internal master clock and must be
provided during both ST-BUS and SSI modes of operation. This is a TTL level input.
In ST-BUS mode the MCLK input (also known as C4i in ST-BUS terms) is derived from the
synchronous 4.096 MHz clock available from the layer 1 transceiver device. The C4i clock,
input to MCLK, is used in this mode as both the internal master clock and for deriving the
C2o output clock and EN1/EN2 output enable strobes.
In SSI mode a 4.096 MHz master clock must be derived from an external source. This
master clock may be asynchronous relative to the 8 kHz frame reference.
2
3
F0i
Frame alignment input pulse for ST-BUS interface operation. This input should be tied low
if ST-BUS operation is not required.
This is a TTL level input.
2.048MHz Clock output for ST-BUS applications. This clock is MCLK divided by 2 and
inverted. The C2o output activity state is governed by the F0i input pin condition.
F0i input
C2o output
V
SS
V
DD
Active F0i strobe
disabled (SSI mode automatically activated)
enabled
enabled and aligned to F0i due to C4i input at MCLK
3
4
C2o
4
5
5
6
DSTo
DSTi
Serial PCM octet output stream. Refer to the serial timing diagram of Figure 12.
Serial PCM octet input data stream. Refer to the serial timing diagram of Figure 12.
This is a TTL level input.
8-18
MS1
MS2
MS3
NC
MS4
A/µ
FORMAT
12
13
14
15
16
17
18
DSTo
DSTi
BCLK
VSS
NC
ENB2
ENB1
4
3
2
1
28
27
26
•
MCLK
F0i
C2o
NC
ENS
EN2
EN1
5
6
7
8
9
10
11
25
24
23
22
21
20
19
ADPCMo
ADPCMi
ENA
VDD
NC
IC
PWRDN
Description
MITEL [ MITEL NETWORKS CORPORATION ]
