Preliminary Information
MT9125
D
X
D
R
V
FxL+
FS
X
V
FxL-
FS
R
BCLK
X
MCLK
X
V
FRO
D
X
D
R
V
FxL+
FS
X
V
FxL-
FS
R
BCLK
X
MCLK
X
V
FRO
V
DD
D
X
D
R
V
FxL+
FS
X
V
FxL-
FS
R
BCLK
X
MCLK
X
V
FRO
D
X
D
R
V
FxL+
FS
X
V
FxL-
FS
R
BCLK
X
MCLK
X
V
FRO
MT8910
T
R
L
in
+
L
in
-
L
out
+
L
out
-
F0b
C4b
DSTo
DSTi
MT9125
C2o
BCLK
F0i
MCLK
ENS
EN1
EN2
S
L
I
C
T
R
ADPCMi
DSTi
ADPCMo DSTo
ENA
ENB1
ENB2
S
L
I
C
T
R
FPi
C4i
DSTi
DSTo
Gate Array
MT9125
C2o
BCLK
F0i
MCLK
ENS
EN1
EN2
S
L
I
C
T
R
Ring
Generator
ADPCMi DSTi
ADPCMo DSTo
ENA
ENB1
ENB2
Hookswitch
from SLICs
to SLICs
S
L
I
C
T
R
Figure 7 - Pair Gain Application (ST-BUS/SSI)
Dout
Din
STB1
CLK
MT8910
T
R
L
in
+
L
in
-
L
out
+
L
out
-
F0b
C4b
DSTo
DSTi
MT9125
C2o
BCLK
F0i
MCLK
ADPCMi
ENS
EN1
EN2
Ain+
Ain-
Aout
2x
S
L
I
C
R
T
R
T
DSTi
ADPCMo DSTo
ENA
ENB1
ENB2
Dual Codec
FPi
C4i
DSTi
DSTo
Gate Array
V
DD
MT9125
C2o
BCLK
F0i
MCLK
ENS
EN1
EN2
Dout
Din
STB1
CLK
Ain+
Ain-
Aout
2x
S
L
I
C
R
T
R
T
Ring
Generator
to SLICs
Hookswitch
from SLICs
ADPCMi
DSTi
ADPCMo DSTo
ENA
ENB1
ENB2
Dual Codec
Figure 8 - Pair Gain Application (ST-BUS/ST-BUS)
8-25
MITEL [ MITEL NETWORKS CORPORATION ]
