MT9123
Preliminary Information
Figure 2 - Pin Connections
Pin Description
Pin #
1
Name
ENA1
Description
SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input).
This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this strobe must be present for frame synchronization. This is an active high channel
enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for Echo Canceller A
on Rin/Sout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENB1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
2
ENB1
SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input).
This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller B on Rin/Sout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENA1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
3
ENA2
SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input).
This pin has dual functions
depending on whether SSI or ST-BUS is selected.
For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller A on Sin/Rout pins. Strobe period is 125 microseconds.
For ST-BUS, this pin, in conjunction with the ENB2 pin, will select the proper ST-BUS mode for
Sin/Rout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.
8-46
LAW
FORMAT
PWRDN
IC3
IC4
S4/SCLK
S3/CS
ENA1
ENB1
ENA2
ENB2
Rin
Sin
VSS
MCLK
IC1
NLP
IC2
LAW
FORMAT
PWRDN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PDIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CONFIG2
CONFIG1
BCLK/C4i
F0i
Rout
Sout
VDD
F0od
S1/DATA1
S2/DATA2
S3/CS
S4/SCLK
IC4
IC3
12
13
14
15
16
17
18
Rin
Sin
VSS
MCLK
IC1
NLP
IC2
4
3
2
1
28
27
26
•
ENB2
ENA2
ENB1
ENA1
CONFIG2
CONFIG1
BCLK/C4i
5
6
7
8
9
10
11
PLCC
25
24
23
22
21
20
19
F0i
Rout
Sout
VDD
F0od
S1/DATA1
S2/DATA2