MT9123
Preliminary Information
C4i
F0i
0
1
2
3
4
F0od
PORT1
Rin
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
ECA
ECB
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Sout
PORT2
Sin
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
ECA ECB
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Rout
outputs=High impedance
inputs = don’t care
indicates that an input channel is bypassed to an output channel
ST-BUS Mode 3 supports connection to 2B+D devices where timeslots 0 and 1 transport D and C channels and both
echo canceller I/O channels are assigned to ST-BUS timeslots 2 and 3. Both PORT1 and PORT2 must be configured in
ST-BUS Mode 3.
Figure 7 - ST-BUS 8 Bit Companded PCM I/O with D and C channels (Mode 3)
C4i
F0i
F0od
Rin
SS S 12 1110 9 8 7 6 5 4 3 2 1 0 S S S 12 1110 9 8 7 6 5 4 3 2 1 0
PORT1
ECA
ECB
SS S 12 1110 9 8 7 6 5 4 3 2 1 0 S S S 12 1110 9 8 7 6 5 4 3 2 1 0
Sout
Sin
S S S 12 1110 9 8 7 6 5 4 3 2 1 0 SS S 12 1110 9 8 7 6 5 4 3 2 1 0
PORT2
ECB
ECA
Rout
S S S 12 1110 9 8 7 6 5 4 3 2 1 0 SS S 12 1110 9 8 7 6 5 4 3 2 1 0
outputs=High impedance
inputs = don’t care
ST-BUS Mode 4 allows 16 bits 2’s complement linear data to be transferred using ST-BUS I/O timing. Note that PORT1
and PORT2 need not necessarily both be in mode 4.
Figure 8 - ST-BUS 16 Bit 2’s complement linear PCM I/O (Mode 4)
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