Preliminary Information
C4i
MT9123
F0i
F0od
0
1
2
3
4
PORT1
Rin
ECA
ECB
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Sout
PORT2
Sin
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
ECA
ECB
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Rout
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
outputs=High impedance
inputs = don’t care
In ST-BUS Mode 1, both echo canceller I/O channels are assigned to ST-BUS timeslots 0 and 1. Note that the user
could configure PORT1 and PORT2 into different ST-BUS modes. The pin F0od is always delayed 4 time slots to permit
a more flexible interleave of ST-BUS modes.
Figure 5 - ST-BUS 8 Bit Companded PCM I/O on Timeslots 0 & 1 (Mode 1)
C4i
F0i
F0od
PORT1
Rin
0
1
2
3
4
ECA
ECB
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Sout
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
PORT2
Sin
ECA
ECB
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Rout
outputs=High impedance
inputs = don’t care
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
In ST-BUS Mode 2, both echo canceller I/O channels are assigned to ST-BUS timeslots 2 and 3. Note that the user
could configure PORT1 and PORT2 into different ST-BUS modes. The pin F0od is always delayed 4 time slots to permit
a more flexible interleave of ST-BUS modes.
Figure 6 - ST-BUS 8 Bit Companded PCM I/O on Timeslots 2 & 3 (Mode 2)
8-57
MITEL [ MITEL NETWORKS CORPORATION ]
